1. Field of the Invention
The present invention relates to a process for manufacturing a multiple layer wiring substrate composed in such a manner that a thin film capacitor element is incorporated onto a substrate on which multiple layers of conductor patterns are formed via insulating layers.
2. Description of the Related Art
Concerning the wiring substrate on which a plurality of electronic parts such as semiconductor elements and semiconductor packages are mounted, in order to enhance the electric characteristics of these parts and circuit, a technique has been proposed by which a thin film capacitor is formed on a multiple layer wiring substrate by applying a substrate manufacturing technique of laminating sheets such as a build-up method or subtractive method. This technique is disclosed in Japanese Unexamined Patent Publication No. 2001-110675, published on Apr. 20, 2001 (corresponding to U.S. patent application Ser. No. 09/679,328) now U.S. Pat. No. 6,498,714. This thin film capacitor is formed as follows. For example, thin films of Ti (titanium) and Ta (tantalum) are successively attached onto a substrate of copper or a wiring layer (lower electrode) so that a metallic film layer is formed. This metallic film layer is subjected to anodic oxidation in an appropriate electrolyte so that a dielectric layer is formed, and then an upper electrode of a thin film of Au (gold) or Cu (copper) is formed on the thus formed dielectric layer by a method of vacuum vapor deposition or a method of sputtering. The reason why the thin film of Ti is attached onto the substrate of copper or the wiring layer is that a barrier layer is formed for suppressing the diffusion of copper ions into the thin film of Ta in the process of anodic oxidation and for preventing copper ions from dissolving into the electrotytic solution and that the adherence strength of the thin film of Ta with respect to the substrate is enhanced.
The thin film capacitor is incorporated onto the copper substrate or wiring layer in the manufacturing process of a multiple layer wiring substrate. Therefore, unless patterning is conducted, a thin metallic layer and anodic oxidation layer are formed on the wiring layer on the entire substrate, and the degree of freedom of designing the wiring on the multiple layer wiring substrate is deteriorated and further there is a possibility that the wiring is short-circuited in the interlayer connection which is accomplished through via holes.
In the case where anodic oxidation is conducted on the copper wiring layer, when pin holes or cracks are caused in a portion of the anodic oxidation film, copper ions are diffused into the thin metallic layer and the insulating property of the oxidation film is lost. Therefore, it becomes impossible to form an oxidation film of a predetermined thickness. The larger the area of the plate of the capacitor is, the higher the rate (percent) of defective anodic oxidation film is. Therefore, the yield is lowered.
The present invention has been accomplished to solve the above problems in the prior art.
It is an object of the present invention to provide a process for manufacturing a multiple layer wiring substrate characterized in that a plurality of thin film capacitors are formed, at the same time, by selectively conducting anodic oxidation in a limited area of the conductor pattern and that the rate (percent) of defective products is reduced.
According to the present invention, there is provided a process for manufacturing a multiple layer wiring board incorporated therein a thin-film capacitor, the process comprising the following steps of:
covering a first conductor pattern formed on an insulating layer, except for a lower electrode forming region of a thin film capacitor, with a first resist film;
forming a metallic film layer consisting of a barrier metal layer and tantalum metal layer, in this order, on an entire face of the first conductor pattern covered with the first resist film;
removing the first resist film to remove the metallic film layer, except for the lower electrode forming region, from a surface of the first conductive pattern;
covering a face of the first conductor pattern, except for the lower electrode forming region of the first conductor pattern, with a second resist film;
forming an anodic oxidation film on the metallic film layer exposed by the second resist film;
removing the second resist film and attaching an adherence layer and a metal seed layer, in this order, on the anodic oxidation film and on the conductor pattern; and
forming a second conductor pattern, which becomes an upper electrode, on the anodic oxidation film.
The upper electrode of the second conductor pattern is formed by attaching the adherence layer and the metal seed layer onto the anodic oxidation film; and forming a thick plated layer on the metal seed layer.
The adherence layer and the metal seed layer are attached onto the anodic oxidation film by a sputtering method.
The thick plated layer is formed on the metal seed layer by subtractive method or semi-additive method.
The process further comprises the following steps of:
laminating an insulating resin layer on the second conductor pattern including the upper electrode;
drilling the insulating resin layer to form a via hole having a bottom thereof on the upper electrode;
via-hole plating to form a conductor layer extending from an inner wall of the via hole to an upper surface of the insulating resin layer; and
etching and patterning the conductor layer to form the second conductor pattern which is connected with the upper electrode.
The metallic film layer is formed by any one of a sputtering method, a chemical vapor phase deposition (CVD) method, and a vapor deposition method.
According to another aspect of the present invention there is provided a process for manufacturing a multiple layer wiring board incorporated therein a thin-film capacitor, the process comprising the following steps of:
forming a metallic film layer consisting of a barrier metal layer and tantalum metal layer, in this order, on a first conductor pattern formed on an insulating layer;
covering a lower electrode forming region of a thin film capacitor in the first conductor pattern attached to the insulating layer with a first resist film;
etching to remove the metallic film layer, where is not covered with the first resist film;
removing the first resist film and covering a face of the first conductor pattern, except for a region on the metallic film layer, with a second resist film;
forming an anodic oxidation film on the metallic film layer exposed from the second resist film;
removing the second resist film and attaching an adherence layer and a metal seed layer, in this order, on the anodic oxidation film and on the first conductor pattern; and
forming a second conductor pattern, which becomes an upper electrode, on the anodic oxidation film.